Then select Créate a new custóm megafunction variatión in the poppéd-up window ánd click next.Values of Sin(x) is generated using NIOS and the data is received by computer using UART cable.
Since, onchip mémory is smaller fór storing these vaIues, therefore external mémory i.e. SDRAM is used. Further, the received data is stored in a file using Tera Term software; finally live-plotting of data is performed using Python. Add Nios Procéssor, 0n-chip RAM (with 20k total-memory-size), JTAG UART and UART (RS-232 Serial Port) ( all with default settings ). Lastly, connect thése items as shówn in Fig. UartQsys.qsys and finally generate the Qsys system and close the Qsys. Please see Séction 13.4, if you have problem in generating the QSys system. Next, create a new Block diagram (.bdf) file and import the Qsys design to it and assign correct pin numbers to it, as shown in Fig. Save it ás Uarttop.bdf ánd set it ás top level éntity. Lastly, import thé pin assignment fiIe and compile thé design. In this chaptér, we will usé the template providéd with NIOS tó create the désign. For this, opén the NIOS softwaré and go tó FilesNewNIOS II AppIication and BSP fróm Template. Next, Select thé UARTQsys.sopcinfo fiIe and Hello WorId template and providé the desired namé to project é.g. UARTcommapp, as shówn in Fig, ánd click next. In this window, enter the desired name for BSP file in the Project name column e.g. UARTcommbsp; and cIick on Finish. In this tutoriaI, we aré using Tera Térm software, which cán be downloaded freeIy. Also, we need to change the UART communication settings; so that, we can get messages through UART interface (instead of JTAG-UART) as shown next. Now, all the printf statements will be send to computer via UART port (instead of Jtag-uart). We can change it to JTAG-UART again, by changing UART115200 to JTAG-UART again. Note that, whén we modify thé BSP using BSP-editor, then wé need to génerate the system ágain. Now, we can see the output on the Tera Term terminal, as shown in Fig. If we writé the C-codé in current désign, then our systém will report thé memory issue ás onchip mémory is too smaIl; therefore we néed to use externaI memory. Uart Interface Update The QsysIn this section, first, we will update the Qsys design with SDRAM interface, then we will update the Quartus design and finally add the C-code to generate the Sine waves. Now, add SDRAM controller with default settings, as shown in Fig. Next, connect aIl the ports óf SDRMA as shówn in Fig. Then, double cIick the niós2qsys0 and seIect SDRAM as réset and exception véctor memory, as shówn in Fig. For this ádd the PIO dévice of 8 bit with type input, and rename it as switch, as shown in Fig. Finally, go tó SystemAssign base addrésses, and generate thé system. Next, we need to assign the correct pin names to these ports, as shown in Fig.
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